1. Field of the Invention
The present invention relates to an oscillation circuit, particularly to speeding-up of an oscillation circuit.
2. Description of Related Art
In recent years, the operating speed of CPUs and memory I/Fs in semiconductor integrated circuits has been progressively increased. Oscillation circuits capable of operating at high speed are used in a wide range of fields, including generation of clock signals for microprocessors and generation of carriers for mobile phones and the like. In this manner, high-speed operable oscillation circuits are essential for large-scale and high-speed data transfer and data processing. Nevertheless, the high-speed operation of the oscillation circuits is hindered by some factors such as an influence of currents which flow while oscillation of oscillation circuits is activated. In addition, it is very difficult to control currents flowing in the oscillation circuits. This being the case, a technology capable of easily controlling the currents flowing in oscillation circuits is demanded in order to enable the oscillation circuits to operate at high speed.
FIG. 7 shows an oscillation circuit described in Japanese Patent Application Publication No. 2001-358565 (JP 2001-358565 A). FIG. 8 shows a circuit configuration of a delay circuit constituting the oscillation circuit shown in FIG. 7. The delay circuit 18 includes: an amplifier (N-channel MOS transistor) 26 and an amplifier (N-channel MOS transistor) 27 which share a transistor (P-channel MOS transistor) 25; an amplifier (N-channel MOS transistor) 29 and an amplifier (N-channel MOS transistor) 30 which share a transistor (P-channel MOS transistor) 28; and a variable current generator (P-channel MOS transistor) 31 and a variable current generator (N-channel MOS transistor) 32 for controlling the amounts of currents flowing in the amplifiers 26, 27, 29, 30. In FIG. 8, reference signs Cs1 (33) and Cs2 (34) denote parasitic capacitances between the output terminals of the delay circuit 18 and the input terminals of another delay circuit at the following stage.
By use of signals inputted through the terminals Vin1, Vin2, the amplifiers 26, 30 and the transistors 25, 28 charge and discharge the parasitic capacitances Cs1, Cs2, and output signals, whose phases are reversed from those of these input signals, to terminals Vout1, Vout2. A positive feedback circuit including the amplifiers 27, 29 is provided to connect the output signals to each other. The gate of the amplifier 27 is connected to an output node where the drain of the transistor 28 and the drain of the amplifier 30 are connected together. The gate of the amplifier 29 is connected to an output node where the drain of the transistor 25 and the drain of the amplifier 26 are connected together.
Thereby, in this positive feedback circuit, the amplifier 27 amplifies a minute potential difference in the signal outputted from the amplifier 30, and outputs the amplified potential difference to an output terminal of the amplifier 26. Similarly, the amplifier 29 amplifies a minute potential difference in the signal outputted from the amplifier 26, and outputs the amplified potential difference to an output terminal of the amplifier 30. In addition, the variable current generator 31 is connected between the power supply voltage VDD, and the sources of the transistors 25, 28. The variable current generator 32 is connected between the ground voltage GND and the transistors 26, 27, 29, 30. In this respect, a current flowing through the variable current generator 31 is controlled on the basis of a voltage of a terminal Vcontp. Furthermore, a current flowing through the variable current generator 32 is controlled on the basis of a voltage of a terminal Vcontn. Thereby, the delay circuit 18 is capable of controlling a delay value of the signal output relative to the signal input.
As described above, even when the potential difference between the signals inputted from the terminals Vin1, Vin2 is minute, the amplifiers 27, 29 detect the signal difference and thus amplify its signal amplitude. Hence, the amplifiers 27, 29 forcedly operate differential pair outputs (voltages of the respective terminals Vout1, Vout2) at a voltage value of the power supply voltage or the ground voltage. In this manner, each delay circuit is capable of increasing its gain. For instance, even if the differential pair inputs to the terminals Vin1, Vin2 are both at the ground level, the amplifiers 27, 29 amplify a minute potential difference which occurs between the differential pair outputs due to device noise and the like. In addition, the amplifiers 27, 29 operate so that the differential pair outputs can be reverse-phase outputs. Furthermore, the amplifiers 26, 27 share the transistor 25, whereas the amplifiers 29, 30 share the load transistor 28. With this configuration, four amplifiers can be formed by use of the 6 transistors.
Next, descriptions will be provided for a configuration shown in FIG. 7. In FIG. 7, delay circuits 18-d, 18-e, 18-f, 18-g each with the configuration shown in FIG. 8 are cascade-connected one after another. An output terminal Vout1 of the delay circuit 18-g in the last stage is connected to an input terminal Vin2 of the delay circuit 18-d. In addition, an output terminal Vout2 of the delay circuit 18-g is connected to an input terminal Vin1 of the delay circuit 18-d. 
Next, descriptions will be provided for an operation of the oscillation circuit shown in FIG. 7. For instance, when signals of an input terminals Vin1 and Vin2 of the delay circuit 18-d are at high level and at low level, respectively, signals of output terminals Vout1 and Vout2 of each of the delay circuits 18-d, 18-e, 18-f, 18-g are also at high level and at low level, respectively. Then, the output signals from the delay circuit 18-g are crossed over, and are thus fed back into the input terminals of the delay circuit 18-d. Specifically, the output terminal Vout1 of the delay circuit 18-g is connected to the input terminal Vin2 of the delay circuit 18-d, whereas the output terminal Vout2 of the delay circuit 18-g is connected to the input terminal Vin1 of the delay circuit 18-d. Consequently, the signal of the input terminal Vin1 of the delay circuit 18-d changes from high level to low level, whereas the signal of the input terminal Vin2 of the delay circuit 18-d changes from low level to high level.
Thereby, signals of the output terminals Vout1 of the delay circuits 18-d, 18-e, 18-f, 18-g sequentially change to the low level, whereas signals of the output terminals Vout2 of the delay circuits 18-d, 18-e, 18-f, 18-g sequentially change to high level. In addition, the feedback changes the signal of the terminal Vin1 of the delay circuit 18-d from low level to high level, and the signal of the terminal Vin2 of the delay circuit 18-d from high level to low level. The oscillation circuit oscillates by repeating this sequence. In this respect, by changing voltages of the terminals Vcontp, Vcontn, a current of each variable current generator in each delay circuit can be controlled, and thereby a delay value of each delay circuit can be controlled. In other words, the oscillation frequency of the oscillation circuit can be controlled.
Here, assume a case where, for instance, signals of the respective output terminals Vout1, Vout2 of the delay circuit 18-d are both at low level in the oscillation circuit according to JP 2001-358565 A shown in FIG. 7. In this case, signals of the output terminals Vout1, Vout2 of the delay circuit 18-e are both at high level; signals of the output terminals Vout1, Vout2 of the delay circuit 18-f are both at low level; and signals of the output terminals Vout1, Vout2 of the delay circuit 18-g are both at high level. In other words, this results in an activation state where the oscillation circuit does not oscillate (an oscillation stop state).
By use of the delay circuit shown in FIG. 8, descriptions will be hereinbelow provided for a setting to avoid the oscillation stop state. When signals of the input terminals Vin1, Vin2 are both at low level, the transistors 25, 28 are turned on. By this, a high-level signal is supplied to the gate of each of the transistors 27, 29. Thereby, the transistors 27, 29 are turned on. In this case, the delay circuit needs to have a circuit configuration in which the output terminals Vout1, Vout2 output signals whose phases are reverse to each other. Specifically, in order to activate oscillation of the oscillation circuit which is currently in the oscillation stop state, the transistor 27 constituting the third amplifier and the transistor 29 constituting the fourth amplifier each need to have a large differential gain. In other words, the transistors 27, 29 need to have a transistor configuration which is capable of sensitively responding to even a minute signal potential difference. In this case, the transistors 27, 29 need to be configured in a large transistor size so as to have a sufficiently large current capability.
Thus, the transistors 27, 29 constitute the differential amplifier for activating the oscillation of the oscillation circuit from the oscillation stop state, and continuously operate even when the oscillation circuit stably oscillates after the oscillation activation. However, the transistors 27, 29 hinder the oscillation circuit from oscillating at high-speed, because the transistors 27, 29 each have the sufficiently large current capability, as described above.
Hereinbelow, descriptions will be provided for a mechanism which causes the foregoing problem by use of FIG. 9. FIG. 9 shows how currents flow in a delay circuit constituting the oscillation circuit described in JP 2001-358565 A. Reference sign Is1 denotes a current flowing through the transistor 25; Is2, a current flowing through the transistor 27; and Iout, an output current flowing to the output terminal Vout2. In addition, reference signs Vin1, Vin2 denote the input terminals of the delay circuit; and reference sings Vout1, Vout2 denote the output terminals of the delay circuit. The transistors 31, 32 shown in FIG. 8 have no influence on the operation, and thus descriptions thereof will be omitted here. Furthermore, for the sake of explanatory convenience, a terminal connected to the sources of the transistors 25, 28 is denoted by reference sign Vpp, and a terminal connected to the sources of the transistors 26, 27, 29, 30 is denoted by reference sign GND.
While the transistor 27 is on, the current Is2 flows through the transistor 27. During this time, the output current Iout flowing to the output terminal Vout2 decreases. In other words, the output current Iout can be expressed with the current Is1 minus the current Is2. In the example shown in FIG. 9, the output current Iout decreases due to the current Is2 flowing when a signal of the output terminal Vout2 changes from low level to high level, that is, when a signal of the output terminal Vout1 changes from high level to low level.
In this respect, as publicly known, the oscillation frequency of the oscillation circuit 1 is proportional to the output current Iout and inversely proportional to the capacitance Cs1. For this reason, as the current Is2 becomes larger, the upper limit of the oscillation frequency becomes lower. In other words, as the current Is2 becomes larger, the speeding-up of the oscillation frequency of the oscillation circuit 1 is more limited. To address this, the current Is2 may be decreased by reducing a channel width W of the transistor 27. Once the current capacity of the transistor 27 is reduced, however, the oscillation circuit would have a difficulty in avoiding the oscillation stop state when activating its oscillation.
In the delay circuit shown in FIG. 8, as described above, a large amount of a current flows through each of the transistors 27, 29 even while the oscillation is stable. This hinders the oscillation circuit from oscillating at high-speed. On the other hand, reduction of the current capacity of each of the transistors 27, 29 by reduction in their transistor size is conceivable as a measure to achieve the speeding up of the oscillation of the oscillation circuit. However, this makes it difficult for the oscillation circuit to avoid the oscillation stop state when activating its oscillation.
As described above, the conventional oscillation circuit has a problem that the speeding up of the oscillation frequency is limited by some factors such as an influence of currents for amplifying oscillation signals.